ADCCCN Maxim Integrated Analog to Digital Converters – ADC CMOS High -Speed 8-Bit A/D Converter with Track/Hold Function datasheet, inventory. ADCCCN/NOPB Texas Instruments Analog to Digital Converters – ADC 8B Hi Spd Compatible A/D Cnvtr datasheet, inventory, & pricing. For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at. , or visit Maxim’s website at
|Published (Last):||6 April 2008|
|PDF File Size:||1.17 Mb|
|ePub File Size:||9.80 Mb|
|Price:||Free* [*Free Regsitration Required]|
When mode is high. In this configuration, a complete conversion is done. By using a half-flash conversion technique, the 8-bit. C unless otherwise specified. Vapor Phase 60 sec.
At this instant the MS comparators go from zeroing to. CS must be low in order for the RD or. The equivalent input circuit of the ADC is shown in. INT going low indicates that the.
Logic Input Threshold Voltage vs. Maximum V IN Input. In RD mode, the input switches are closed for approximately. Following another ns, the lower 4 bits are recov.
Connection and Functional Diagrams. Although the conversion time for the ADC is. I IN 0Logical “0”. Minimum V REF. RD going low, also RD will enable the.
As R S increases, it will take longer for the input. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. The voltage at V REF – sets the. The comparators’ outputs are not latched while WR is. MS means most significant.
Description of Pin Functions. After ns, data from the. This reference flexibility lets the input span not only be varied. In the first cycle, one input switch and the inverter’s feedback. For ease of interface to microprocessors, the ADC has. This is an open drain output no. ADC does not “look” at the input when these transients. Total unadjusted datasgeet includes offset, full-scale, and linearity errors. A critical component is any component of a life.
ESD Susceptability Note 9. Here, a conversion is started with the WR. Due to the unique conversion techniques employed by the.
ADC Technical Data
This analog signal is then subtracted. INT and can exercise a read after only ns Figure 9. This device in effect now has one differential input pair. In addition, about 12 pF of input stray capacitance.